Instantaneous incremental compiler for producing logic circuit designs

ABSTRACT

A computer aided logic design system for instantaneously compiling circuit component entries into a schematic model which provides immediate simulation of each entry or deletion into the electronic circuit schematic. The system includes software for processing logic designs which produces a signal table for storing all inputs and outputs of chips stored in a specification table. The processor also produces a call table that lists all chips from the chips specification table from which chip models can be retreived and executed. Additionally, a software routine produces a netlist transfer table that specifies the transfer of signals within the signal table produced by software processing, which correspond to the signal distribution in the circuit being designed. After production of the signal table, specification table, call table and netlist transfer table, a software processing routine executes sequential values retrieved from the call table and netlist transfer table to create a second signal table which is compared with the first signal table. The software processing routine continuous to execute values retrieved from the call table and netlist transfer table and compare the first and second signal tables until both the second signal table being created is identical with the first signal table stored in memory. The software processing means also includes a delay which delays sequential processing until the comparing step for comparing the second signal table with the first signal table reaches a stable state.

FIELD OF THE INVENTION

The present invention relates to computer aided generation of componentsfor schematic entry and timing simulation, and more particularly relatesto a system design means and method for instantaneous generation andcompilation of schematic entry and automatic generation of designtiming.

BACKGROUND OF THE INVENTION

The art of schematic entry is well established. The majority of computeraided engineering work stations allow the user to enter the graphicalrepresentations for such elements as integrated circuits, resistors,capacitors and connecting lines. Then these entries are compiled in abatch mode to produce computer meaningful data such as an elementconnectivity list, a parts list, an error report and simulation data.

The major disadvantage of this process is that design compilation takesa long time and is proportional to the size of the schematic. Also, eventhe smallest design correction requires the entire schematic to berecompiled anew. This process results in schmematic capture softwarethat is time consuming and inconvenient to use particularly when thereare numerous design changes.

Another disadvantage of the present schematic capture software is thatany design error shows up only after batch compilation of the schematic,which is late in the design process.

Still another disadvantage of the present methods is that the logicsimulation of the schematic design can take place only after schematicbatch compilation, creating a large time delay between the schematicentry or correction and observation of its effect on the systembehavior.

The biggest disadvantage of the present computer aided engineering workstations is that they are labor intensive and incapable of providingfully automated timing analysis of the logic design. The work stationscan only provide the mini-max analysis that calculates the zones ofuncertainty in the combinatorial circuits, which are used in a greatmajority of logic designs. Furthermore, the present work stations cannotcalculate the digital noise filtering properties of logic devices, whichis mandatory to effectively model the circuit's behavior.

BRIEF DESCRIPTION OF THE INVENTION

It is one object of the present invention to improve computer generationof the design entry and simulation and make it free from theaforementioned limitations. Specifically, it is an object of the presentinvention to instantaneously compile each schematic entry and providefor immediate simulation of each schematic entry or deletion.

Another object of the present invention is to automate the designsimulation process by statistical analysis of a multiplicity of printedcircuit boards automatically generated in software, wherein each boardhas components with randomly selected propagation delay values.

Another object of the present invention is to provide means forautomatic filtering of noise signals created either by logic elements,radiation, or other sources.

While the specification concludes with claims that distinctly specifyand claim the subject matter which is regarded as the invention, it isbelieved that the novel features and advantages of the invention will bemore fully understood from the following detailed description inconjunction with the accompanying drawings in which:

DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a typical logic schematic diagram.

FIG. 2 is a flowchart of incremental compilation.

FIG. 3 is a flowchart for software processing of random data.

FIG. 4 is a timing diagram graph illustrating noise filtering.

DESCRIPTION OF THE PREFERRED EMBODIMENT

As shown in the schematic diagram of FIG. 1, a typical logic circuitincludes NAND gate 1, OR gate 2, input connector (J1) 3, outputconnector (J2) 4, and connecting lines 5, 6, 7, 8 and 9. The algorithmfor processing a logic circuit schematic entry is shown in FIG. 2. Inputactivity softwate 11 detects if there has been any keyboard, mousedevice, or similar input activity from input device 10. If inputactivity has been detected by subroutine 11, subroutine 12 checkswhether the activity was an integrated circuit related entry. To savememory and speed up processing, only actually used IC (integratedcircuit) models are loaded into RAM (random access memory) and the ICmodels are then used by call instructions to simulate integratedcircuits of the same type.

Subroutine 13 checks to see if each newly entered component chip has anequivalent model already loaded into RAM. If the IC model has not beenused before; and is not yet in an IC Model Table, subroutine 14 willload that IC model from storage into the RAM based IC Model Table. Thesubroutine 15 keeps track of all schematic entered integrated circuitsby means of a Chip Table that stores the integrated circuits by circuitnames, and addresses of their IC models that are located in the IC ModelTable.

                  IC MODEL TABLE                                                  ______________________________________                                                                 ABSOLUTE                                             IC TYPE      SUBROUTINE  ADDRESS                                              ______________________________________                                        00           MOV al, [P1]                                                                              aa1                                                               NOT al                                                                        MOV ah, al                                                                    MOV al, [P2]                                                                  NOT al                                                                        OR al, ah                                                                     MOV [P3], al                                                     32           MOV al, [P1]                                                                              aa2                                                               OR al, [P2]                                                                   MOV [P3], al                                                     ______________________________________                                    

P1, P2, and P3 are parametric variables, replaced by call instructionswith signal addresses fromthe Signal Table.

                  CHIP TABLE                                                      ______________________________________                                        SCHEMATIC  MODEL             GRAPHICS                                         IC NAME    ABSOLUTE ADDRESS  DATA                                             ______________________________________                                        IC1        aa1               XYZ1                                             IC2        aa2               XYZ2                                             ______________________________________                                    

The Chip Table contains the IC circuit or schematic name, (e.g. IC1),and absolute address of its chip model location in the IC Model Table.In addition, the Chip Table contains graphics information about the ICconnectivity and geometrical location of the chip on the schematic, andwhat sections of the chip are already in use.

If the input activity, as detected by the subroutine 16, was a drawconnection command, then the graphics table that contains all linedrawing information is updated by software subroutine 17. The graphicstable is used to create netlist data and screen drafting.

If the input activity is neither a chip entry nor a line drawing then itis checked by subroutine 18 if it is simulation related. If subroutine18 detects the start of the simulation process then it directssubroutine 19 to create a Signal Table that contains RAM space for eachconnector pin and each IC input and output pin. In addition, it reservesRAM space for each IC model variable that has to be carried from onesimulation cycle to another, like the status of a clock and similarinformation.

                  SIGNAL TABLE                                                    ______________________________________                                                            ABSOLUTE   RELATIVE                                       IC-I/O                                                                              PIN/SIGNAL    ADDRESS    ADDRESS                                        ______________________________________                                        J1    IN1           a1         R1                                             J1    IN2           a2         R2                                             J1    IN3           a3         R3                                             IC1   x1            a4         R4                                             IC1   x2            a5         R5                                             IC1   x3            a6         R6                                             IC2   y1            a7         R7                                             IC2   y2            a8         R8                                             IC2   y3            a9         R9                                             J2    OUT            a10        R10                                           ______________________________________                                    

Subroutine 20 creates an IC Call Table that contains the startingaddress of the IC model in the aforementioned IC Model Table as createdby subroutine 14. In addition, it uses the relative addresses from theSignal Table to provide full specification of the call to process theselected IC.

                  CALL TABLE                                                      ______________________________________                                        IC      DS REGISTER  CALL                                                     ______________________________________                                        IC1     aa1          P1=R4, P2=R5, P3=R6                                      IC2     aa2          P1=R7, P2=R8, P3=R9                                      ______________________________________                                    

Call instructions from the Call Table use the chip models at relativelocations aa1 and aa2, with the substitute logic values found atcorresponding RAM locations R4, R5, R6, R7, R8, and R9.

The schematic compiler according to the present invention firstprocesses each logic chip and then distributes the result of theprocessing through the logic schematic circuit. To facilitate efficientdata distribution through the schematic circuit, a Netlist TransferTable is created by software subroutine 21. The Netlist Transfer Tablespecifies how the data should be transferred within the Signal Table torepresent the schematic netlist data transfer.

                  NETLIST TRANSFER TABLE                                          ______________________________________                                                FROM  TO                                                              ______________________________________                                                IN1   X1                                                                      IN2   X2                                                                      X3    Y1                                                                      IN3   Y2                                                                      y3    OUT                                                             ______________________________________                                    

Software subroutine 22 initializes the Signal Table, with all signalsset to logical 0. Software subroutine 23 performs one simulation cycleby executing the Call Table and Netlist Transfer Table. Following this,software subroutine 23 compares the new IC outputs with the previousones by means of comparing the new Signal Table with the previous one.If the simulation process has resulted in even a single differencebetween the new Signal Table and the previous one, the simulationprocess is repeated until a stable condition within the circuit of FIG.1 is achieved. Subroutine 24 counts how many simulations have beenperformed to stabilize the simulated circuit. If the number ofsimulations exceeds an arbitrarily selected number, larger than 10, thenthe circuit is considered unstable and rejected from further processingby software 25.

If the simulated circuit is stable, subroutine 28 checks if test vectorsfed into the simulated circuit have been completed. If the test vectorshave not been completed, the simulation continues and software 26 feedsnew test vector signals into Signal Table addresses that represent inputsignals to the logic circuit schematic. Next, software subroutine 23performs the aformentioned simulation and the process continues untileither all test vectors are finished, as detected by software subroutine28, or the circuit is determined to be unstable by software subroutines24 and 25.

The existing techniques for simulation of logic designs are based oncalculating minimum and maximum integrated circuit propagation delays.These techniques suffer from unrealistic circuit behavior evaluationsand do not take into account the digital filtering properties of thelogic circuits that drastically minimize the effect of design glitches.Table 1 shows minimum, average, and maximum propagation delays of theintegrated circuits shown in logic circuit schematic of FIG. 1. They canbe either direct catalog data, or load and temperature dependentpropagation delay values, as calculated from appropriate equations notthe subject of the present invention. Normally, Table 1 values would beused for calculating the timing behavior of the logic circuit of theschematic of FIG. 1. However, the present invention introduces a newmethod of logic circuit simulation, depicted by FIG. 3 and FIG. 4 and aModified Call Table.

                  TABLE 1                                                         ______________________________________                                        Timing Model Table                                                                     MINIMUM          MAXIMUM                                                      PROPAGATION      PROPAGATION                                                  (nanoseconds)    (nanoseconds)                                                  Rising  Falling    Rising                                                                              Falling                                   IC MODEL   Edge    Edge       Edge  Edge                                      ______________________________________                                        74LS00     5       3          22    15                                        74LS32     7       7          22    22                                        74AS20     1       1           5    4.5                                       ______________________________________                                    

                  TABLE 2                                                         ______________________________________                                        Quantized Model Table                                                                  MINIMUM          MAXIMUM                                                      PROPAGATION      PROPAGATION                                                  (nanoseconds)    (nanoseconds)                                                  Rising  Falling    Rising                                                                              Falling                                   IC MODEL   Edge    Edge       Edge  Edge                                      ______________________________________                                        74LS00     2       1          11    8                                         74LS32     3       3          11    11                                        74AS20     0       0           3    3                                         ______________________________________                                    

                  TABLE 3                                                         ______________________________________                                        Random Circuit Table                                                          (Randomly Selected/Quantized IC Propagation Delays)                           IC CIRCUIT                                                                              RANDOM PROPAGATION DELAY (nsec)                                     NAME      Rising Edge     Falling Edge                                        ______________________________________                                        IC1 (74LS00)                                                                            3               3                                                   IC2 (74LS32)                                                                            8               9                                                   ______________________________________                                    

FIG. 3 shows a software subroutine for converting the absolute timingvalues in Table 1 into quantized and randomized timing values in Table 2and Table 3 respectively. Software subroutine 31 accepts timequantization entry (e.g. 2 nanoseconds) that represents the minimum timeincrement used in timing analysis and feeds it into software 32 thatdivides the propagation delays in Table 1 by the time quantizationentry. As a result of this arithmetic operation, a new table ofquantized propagation delays is created. Table 2 represents Table 1 withtable quantization of 2 nanoseconds. The calculations are preferablyrounded off to the nearest natural number that is outside of theminimum-maximum propagation delay range listed in Table 1, rather thansimply rounding off to the nearest natural number. Since ach productionprinted circuit board has integrated circuits with propagation delaysthat are random values from the quantized minimum-maximum range of Table2, the printed circuit simulation model should have similar randomlyselected propagation delays. The process of generating random numbers isdescribed in numerous technical publications, therefore, it is notdescribed in detail here. Software subroutine 33 produces the randomnumber for the simulated logic circuit of FIG. 1 and can use eitherMonte Carlo, normal distribution, or other methods of generating arandom number.

The randomly selected propagation delays for gates 1 and 2 are shown inTable 3. These random numbers can be used to insert the appropriatenumber of delay lines into the the outputs of gates 1 and 2. However, aconsiderable increase in processing speed is achieved by using timecounters intstead of delay lines. Time counters count the predeterminedtime delays shown in Table 3 and sample functional gate IC1 and IC2outputs when the time counter reaches the specified state, such as carryor overflow. The sampled outputs are processed and stored in the SignalTable under control of software subroutine 23.

To detect a change on the output of integrated circuits, such as IC1, orIC2, software subroutine 23 compares the previous logic device outputsignal, as listed in the Signal Table, with the newly calculated oneduring execution of the Netlist Transfer Table. The rising edges andfalling edges can drive separate time counters if the modeled integratedcircuit, such as IC1, or IC2, have different rising and falling edgepropagation delays. Equations (1) and (2) show in detail how the risingand falling output edge for gate 1 is detected. REIC1CTR is the risingedge condition and FEIC1CTR is the falling edge condition for gate IC1.Expression X3(-1) stands for the past simulation cycle signal status,saved in Signal Table, and X3 is the current output signal from gate 1.

    REIC1CTR=-X3(-1)*X3                                        (1)

    FEIC1CTR=X3(-1)*-X3                                        (2)

    X3=-(X1*X2)                                                (3)

Software subroutine 35 modifies the Call Table to include the ICpropagation delay model which is created under control of softwaresubroutine 34, by randomly selecting quantized propagation delay numbersfrom Table 3 for each IC in the logic circuit of FIG. 1. Table 4 showsshoftware subroutine 35 modified Call Table.

                  TABLE 4                                                         ______________________________________                                        Modified Call Table                                                           IC    DS REGISTER  CALL                                                       ______________________________________                                        IC1   aa1          P1=R4, P2=R5 P3=R6;                                                           calculate equations (1) and (2).                                              Preset RIC1CTR if REIC1CTR=1                                                  Preset FIC1CTR if FEIC1CTR=1                                                  Store P3 at R6 if RIC1CTR or                                                  FIC1CTR overflows                                                             Decrement RIC1CTR and FIC1CTR                              ______________________________________                                    

The above call software calculates the current output signal X3 andchecks for rising and falling edtes in the signal X3 by means ofequations (1) and (2). If there has been any change in the output signalX3 from the previous simulation cycle, the time counters RIC1CTR andFIC1CTR are preset to the initial count. If there has been no X3 signalline change, the call software checks if the time counters RIC1CTR andFIC1CTR are having overflow. If there has been an overflow propagationdelay timeout 10 call software loads the calculated X3 output signalvalue in the new Signal Table. Otherwise, call software decrements thetime counters and the previous gate 1 output X3(-1) is loaded into thenew Signal Table. A further insight can be gained by referring to FIG.4, depicting gate 1 response to waveforms X1 and X2. Waveform X3 depictsgate 1 output as calculated from equation (3); and X3s represents awaveform that is loaded by call software under control of the timecounters RIC1CTR and FIC1CTR. Time counter FIC1CTR is set to 3 at timet1 due to the falling edge of X3, which is detected by equation (2).Every time counter FIC1CTR is preset to the initial state, counterRIC1CTR is disabled from counting. At t2, counter RIC1CTR is preset to acount of 3, this time by the rising edge of X3 and as detected byequation (1). At the same time, time counter FIC1CTR is disabled fromcounting. At t3 counter FIC1CTR is again preset to a count of 3 byequation (2). If either RIC1CTR of FIC1CTR counter (time counter) hasreached overflow between t1 and through t6, then during each of thesesimulation clock cycles the output X3(-1) from the old signal table iscopied directly into the new signal table. Time counter FIC1CTR reachesoverflow at time t7 and at that time values of X3s, is calculated fromequation (3) and is loaded into the new signal table.

As can be seen from FIG. 4, gate 1 with random propagation delay of 6nanoseconds, represented by a count of 3, did not react to the 2nanosecond spikes on its inputs at time t1 and t2. This feature of thepresent invention automatically eliminates any signal noise that isshorter in duration than the propagation delay of the integratedcircuit. As a result the digital schematic, when simulated by thepresent invention behaves like a digital signal filtering circuit.

This invention is not to be limited by the embodiment shown in thedrawings and described in the description, which is given by way ofexample and not of limitation, but only in accordance with the scope ofthe appended claims.

What is claimed is:
 1. A system for integrated circuit design andsimulating operation comprising;storage means for storing behavorialmodels of integrated circuit chips; first circuit processing means forselecting one or more integrated circuit models from said storage means;automatic drawing means for automatically drawing inputs and outputs ofsaid selected integrated circuit models to produce integrated circuitdesign data; simulating means for simulating inputs and outputs to andfrom said integrated circuit design; second storage means storing tablesof electronic component specifications; said tables including:a signaltable storing all inputs and outputs of said integrated circuit models;a call table storing the relative locations of said integrated circuitmodels for instant recall and execution; a netlist transfer table forspecifying the transfer of signals within said signal tablecorresponding to the signal distribution of the electronic circuit beingdesigned; said simulating means including processing means forproducing, updating and storage in said signal table, said call tableand said netlist transfer table; initializing means for initializingsaid signal in said table; said simulating means performing a simulationcycle by executing values from said call table and said netlist transfertable; said simulation means repeating the simulation cycle until saidintegrated circuit design being created achieves a stable state; wherebyfunctional models of an electronic circuit can be created andinstantaneously tested.
 2. The system according to claim 1 in which saidsimulation means determines a stable state by repeatedly comparing anupdated signal table with the previously updated signal table until theyare identical.
 3. The system according to claim 2 including delay meansand for delaying the next execution of a simulation from said call andtransfer tables until the integrated circuit design being testedachieves a stable state.
 4. The system according to claim 3 includingpropagation delay inserting means for inserting compensation forpropagation delays in said integrated circuit design.
 5. The systemaccording to claim 4 in which said propagation delay inserting meanscomprises means for generating a quantized propagation delay table;means for generating a table of randomly selected propagation delays;delay setting means for setting said delay means according to therandomly selected propagation delays in said table; and modifying meansfor modifying said call table with said propagation delays from saidrandom propagation delay table.
 6. The system according to claim 2including rejection means for rejecting said integrated circuit designfrom further processing if more than a selected number of simulationcycles have occured without said integrated circuit design achieving astable state.
 7. The system according to claim 6 in which said rejectingmeans includes counting means counting the number of simulation cycles;and means for stopping the simulation processing if the number ofsimulation cycles exceeds a predetermined number.
 8. A method ofdesigning a circuit and simulating operating comprising;storingbehavorial models of integrated circuit chips; selecting one or moreintegrated circuit models from said storage means; automatically drawinginputs and outputs to said selected integrated circuit models to produceintegrated circuit design data; simulating inputs and outputs to andfrom said integrated circuit design; storing tables of electroniccomponent specifications; said tables including:storing all inputs andoutputs of said integrated circuit models in a signal table; storing therelative locations of said integrated circuit models for instant recalland execution in a call table; generating a netlist transfer table forspecifying the transfer of signals within said signal tablecorresponding to the signal distribution of the electronic circuit beingdesigned; processing the inputs and outputs of said simulation forproducing, updating and storage in said signal table, said call tableand said netlist transfer table; initializing said singal in said signaltable; performing a simulation cycle by executing values from said calltable and said netlist transfer table; repeating the simulation cycleuntil said integrated circuit design being created achieves a stablestate; whereby functional models of an electronic circuit can be createdand instantaneously tested.
 9. The method according to claim 8 in whichsaid simulation processing determines a stable state by repeatedlycomparing an updated signal table with the previously updated signaltable until they are identical.
 10. The method according to claim 9including delaying the next execution of a simulation from said call andnetlist transfer tables until the integrated circuit design being testedachieves a stable state.
 11. The system according to claim 10 includinginserting for propagation delays in said integrated circuit design. 12.The method according to claim 11 in which said inserting of saidinserting for propagation delay comprises generating a quantizedpropagation delay table; generating a table of randomly selectedpropagation delays; setting delay means in said integrated circuitdesign according to the randomly selected propagation delays in saidtable; and modifying said call table with said propagation delays fromsaid random propagation delay table.
 13. The method according to claim12 including rejecting said integrated circuit design from furtherprocessing if more than a selected member of simulation cycles haveoccured without said integrated circuit design achieving a stable state.14. The method according to claim 13 in which said rejection stepincludes counting the number of simulation cycles; and stoppingsimulation processing if the number of simulation cycles exceeds apredetermined number.